1. Field of the Invention
The present invention relates generally to a semiconductor device and methods thereof, and more particularly, to a redundancy program circuit and methods thereof.
2. Description of Related Art
A fabrication of a semiconductor device (e.g., a semiconductor memory device) may include various tests (e.g., of chips or memory devices on a wafer) to verify a correct function of the semiconductor device. For example, such tests may verify whether circuit devices in the semiconductor device may operate in conformity with a given specification or protocol. In an example test, a plurality of test parameters may be used to check electrical characteristics and/or an operation of a tested semiconductor device. If the given test indicates an incorrect operation of the tested semiconductor device (e.g., because the electrical characteristics and/or the operation of the semiconductor may not be proper), a debugging of the semiconductor device may not be possible.
However, in an example where the semiconductor device may include a defective memory cell within a memory cell array, a repair process (e.g., debugging process) may be executed which may replace the defective memory cell with a redundancy memory cell. In other words, if a portion of the memory cells in the semiconductor device are defective, the defective portion of the memory cells may be replaced with at least one spare memory cell manufactured redundantly, which may thereby enable the semiconductor device to operate correctly.
A redundancy program circuit, which may be alternatively referred to as a fuse box or spare circuit, may be employed to achieve the above described debugging or defective memory cell replacement process. The redundancy program circuit may employ a process which may include melting fuses (e.g., with a high energy light, a laser, etc.), as will be described below in greater detail with reference to FIG. 1.
FIG. 1 illustrates a block diagram of a conventional semiconductor device 107. The conventional semiconductor device 107 may include a memory cell array 40 having a normal memory cell array 41 and a spare memory cell array 42. The normal memory cell array 41 and the spare memory cell array 42 may be connected to row decoders 20, 21, 22, 23, a spare row decoder 25, column decoders 30 and 31 and a spare column decoder 35. Row decoders 20, 21, 22 and 23 and column decoders 30 and 31 may be associated with the normal memory cell array 41, and the spare row decoder 25 and the spare column decoder 35 may be associated with the spare memory cell array 42.
In FIG. 1, a conventional redundancy operation may be performed by a row spare circuit 10 and/or a column spare circuit 11, which may collectively function as the above-described redundancy program circuit. The row spare circuit 10 may receive a pre-decoded row address DRAi from a row predecoder 6 and may generate a row redundancy enable signal X-RENi. The row redundancy enable signal X-RENi may be received by the spare row decoder 25, which may perform a debug in a row direction based on the received row redundancy enable signal X-RENi. Likewise, the column spare circuit 11 may receive a pre-decoded column address DCAi of a column predecoder 7 and may generate a column redundancy enable signal Y-RENi. The column redundancy enable signal Y-RENi may be applied to the spare column decoder 35, which may perform a debug in a column direction based on the received column redundancy enable signal Y-RENi.
FIG. 2 illustrates an applied path of a decoding address applied to the row/column spare circuits 10/11 in the semiconductor device 107 of FIG. 1. For example, if a 7-bit external address EADDi is applied to an address buffer 2, row and column internal address generators 4/5 may each generate an applied bit signal and a complementary signal, the complementary signal inverted from a logic level of corresponding bits of the 7-bit external address EADDi, to generate a 14-bit internal addresses IRAi and ICAi.
The row/column internal address generators 4/5 may be integrated such that an internal address (e.g., a row or column address) may be generated. The row/column predecoder 6/7 may predecode the internal address and may generate, for example, a predecoded address having 16 bits (e.g., DA01 4 bit+DA234 8 bit+DA56 4 bit). The row decoder 20 may decode the predecoded row address DRAi and may select a given word line from among the word lines WL0:n of the normal memory cell array 41 and the row spare circuit 10 may generate a row redundancy enable signal X-RENi for replacing a given row of a defective memory cell in response to the predecoded row address DRAi.
Similarly, the column decoder 30 may decode the predecoded column address DCAi, and may select a given column selection line from among a plurality of column selection lines of the normal memory cell array 41. The column spare circuit 11 may generate a column redundancy enable signal Y-RENi for replacing a given column of a defected memory cell in response to the predecoded column address DCAi.
Referring to FIG. 2, lines of predecoded addresses applied to the decoders 20/30 and the row/column spare circuits 10/11 may be divided into lines L1, L2 and L3. If a circuit (e.g., spare circuit 10, spare circuit 11, etc.) with a decoder includes a NAND gate and an inverter, NMOS transistors within the NAND gate may be influenced by a body effect. The body effect may cause the circuit to be unstable.
FIG. 3 illustrates the conventional row/column spare circuit 10/11 of FIG. 1. The row/column spare circuit 10/11 may include a master fuse circuit (MFC), NMOS transistors N1-N16, a plurality of fuses F1-F16, operating enable transistors M1/M2/M3 and an AND gate AND1. A master fuse MF may be included within the master fuse circuit MFC. The fuses F1-F16 may store addresses of a defective memory cell in order to perform a redundancy operation. In an example, the fuses F1-F16 may include a silicon material (e.g., polysilicon). The fuses F1-F16 may be cut (e.g., melted, cut, opened by a high energy light such as a laser, etc.). The fuses F1-F16 may be disposed in a peripheral circuit region on a chip (e.g., row/column spare circuit 10/11).
If the normal memory cell array 41 includes a defective memory cell and a row and/or column address for designating the defective memory cell is applied (e.g., during operation), the row spare circuit 10 and/or column spare circuit 11 may output a redundancy enable signal RENi to disable a row and/or column of the defective memory cell and may enable a row or column of a redundant memory cell (e.g., based on a cutting of the fuses F1-F16). In an example, referring to FIG. 3, if a memory cell corresponding to an external address “0000000” is determined to be defective (e.g., in a test process), master fuses MF and fuses F2-F4, F6-F12 and F14-F16 may be cut or blown by a fuse cutting or blowing process. Fuses F1, F5 and F13 may not be cut. A redundancy enable signal RENi may be outputted from an AND gate AND1 at a first logic level (e.g., a higher logic level, a lower logic level, etc.) when the external address is applied as “0000000”.
If a normal disable signal at a second logic level (e.g., a lower logic level, a higher logic level, etc.) is applied to the row/column decoder 20/30, the row/column decoder 20/30 may disable a corresponding normal row or normal column. A row or column of a defective memory cell may be set at an inoperable state (e.g., not capable of a reading or writing to/from the memory). The redundancy enable signal RENi may also be applied to a spare row/column decoder 25/35. A row or column of the spare memory cell may be enabled and the defective memory cell may be replaced with a redundant spare memory cell.
In other words, a defective memory cell may be replaced by cutting or blowing a master fuse among fuses MF and F1-F16 in the row/column spare circuits 10/11 and a fuse corresponding to an address bit of the defective memory cell.
In the above-described conventional redundancy program operation, a manufacturing yield of semiconductor devices may be increased by repairing a defective memory cell. However, a chip size and a duration of the redundancy program operation may scale with a number of fuses. For example, if the conventional semiconductor device 107 requires additional memory, it may also require additional fuses for the redundancy program operation (e.g., because more bits may be needed to address the additional memory), thereby requiring a larger chip size which may reduce a yield of the semiconductor device 107 and induce a longer duration for each defective memory cell replacement (e.g., because multiple fuses may be cut/blown), thereby reducing a speed of operation.
Further, the fuses F1-F16 of FIG. 3 may be disposed corresponding to address bits before decoding (e.g., one fuse may be associated with each predecoded address bit). By disposing fuses F1-F16 as corresponding to address bits prior to decoding, a number of fuses in the semiconductor device 107 may be reduced. However, the disposition of the fuses F1-F16 in FIG. 3 may require that address lines be independently added (e.g., the address lines may not be shared), which may increase a complexity of the conventional semiconductor device 107.